--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   22:21:34 04/19/2011
-- Design Name:   
-- Module Name:   /home/goofy/Pulpit/UCiSW2_projekt/recorder_test_bench.vhd
-- Project Name:  WAVE_Recorder
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Recorder
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY recorder_test_bench IS
END recorder_test_bench;
 
ARCHITECTURE behavior OF recorder_test_bench IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Recorder
    PORT(
         CLOCK : IN  std_logic;
         START_RECORDING : IN  std_logic;
         ADC_BUSY : IN  std_logic;
         RS232_BUSY : IN  std_logic;
         CHANNEL_A : IN  std_logic_vector(15 downto 0);
         CHANNEL_B : IN  std_logic_vector(15 downto 0);
         GAIN_0 : IN  std_logic;
         GAIN_1 : IN  std_logic;
         GAIN_2 : IN  std_logic;
         GAIN_3 : IN  std_logic;
         LED_0 : OUT  std_logic;
         LED_1 : OUT  std_logic;
         LED_2 : OUT  std_logic;
         LED_3 : OUT  std_logic;
			LED_RS232_ERROR : out STD_LOGIC;
         ADC_GAIN_INIT : OUT  std_logic;
         ADC_RECORD_SAMPLE : OUT  std_logic;
         GAIN_OUT : OUT  std_logic_vector(7 downto 0);
         RS232_DATA_SEND : OUT  std_logic;
         RS232_DATA : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal CLOCK : std_logic := '0';
   signal START_RECORDING : std_logic := '0';
   signal ADC_BUSY : std_logic := '0';
   signal RS232_BUSY : std_logic := '0';
   signal CHANNEL_A : std_logic_vector(15 downto 0) := (others => '0');
   signal CHANNEL_B : std_logic_vector(15 downto 0) := (others => '0');
   signal GAIN_0 : std_logic := '0';
   signal GAIN_1 : std_logic := '0';
   signal GAIN_2 : std_logic := '0';
   signal GAIN_3 : std_logic := '0';

 	--Outputs
   signal LED_0 : std_logic;
   signal LED_1 : std_logic;
   signal LED_2 : std_logic;
   signal LED_3 : std_logic;
	signal LED_RS232_ERROR : std_logic;
   signal ADC_GAIN_INIT : std_logic;
   signal ADC_RECORD_SAMPLE : std_logic;
   signal GAIN_OUT : std_logic_vector(7 downto 0);
   signal RS232_DATA_SEND : std_logic;
   signal RS232_DATA : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant CLOCK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Recorder PORT MAP (
          CLOCK => CLOCK,
          START_RECORDING => START_RECORDING,
          ADC_BUSY => ADC_BUSY,
          RS232_BUSY => RS232_BUSY,
          CHANNEL_A => CHANNEL_A,
          CHANNEL_B => CHANNEL_B,
          GAIN_0 => GAIN_0,
          GAIN_1 => GAIN_1,
          GAIN_2 => GAIN_2,
          GAIN_3 => GAIN_3,
          LED_0 => LED_0,
          LED_1 => LED_1,
          LED_2 => LED_2,
          LED_3 => LED_3,
			 LED_RS232_ERROR => LED_RS232_ERROR,
          ADC_GAIN_INIT => ADC_GAIN_INIT,
          ADC_RECORD_SAMPLE => ADC_RECORD_SAMPLE,
          GAIN_OUT => GAIN_OUT,
          RS232_DATA_SEND => RS232_DATA_SEND,
          RS232_DATA => RS232_DATA
        );

   CLOCK <= not CLOCK after 20 ns;
	START_RECORDING <= '1', '0' after 40 ns;
	CHANNEL_A <= "1000001100000000";
	CHANNEL_B <= X"0000";
	GAIN_0 <= '1';
	GAIN_1 <= '0';
	GAIN_2 <= '0';
	GAIN_3 <= '0';
	ADC_BUSY <= '0', 
			'1' after 40 ns, 
			'0' after 540 ns, 
			'1' after 580 ns,
			'0' after 1080 ns;
	RS232_BUSY <= '0', '1' after 1220 ns, '0' after 1260 ns;
END;
